PRN: Global 450Mm/Copper/Low-K Convergence Timing, Trends, Issues, Market Analysis 2017 - Research and Markets

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Global 450Mm/Copper/Low-K Convergence Timing, Trends, Issues, Market Analysis 2017 - Research and Markets


DUBLIN, May 15, 2017 /PRNewswire/ --

Research and Markets has announced the addition of the "450Mm/Copper/Low-K Convergence: Timing, Trends, Issues, Market Analysis" report to their offering.

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A semiconductor foundry capable of processing 450mm wafers offers a tremendous economy of scale versus facilities working with smaller-diameter wafers, albeit with large startup costs required for the needed wafer-handling equipment. The larger wafers yield more semiconductor die, assuming that good material quality can be maintained across the surface of the larger wafers. As a rough approximation, only about one-half the wafer starts are required for a 450mm wafer facility compared to a 300mm wafer facility to produce the same number of die.

ASML, one of the major equipment suppliers to chip factories, recently decided to stop trying to develop a new generation of machines that could handle 450mm wafers. No one is definitively ruling out 450mm, but even Intel agrees that it is on hold until the end of the decade. TSMC is not as vocal as Intel, but the Taiwan foundry giant is still interested in 450mm, as well. Still others believe 450mm fabs could get pushed out to the 2020 to 2025 timeframe. Now that work is on hold, along with the Intel investment in ASML's 450mm program.

Equipment makers need a timely decision in order to move forward with their 450mm tool R&D efforts. This report addresses the timeline of 450mm acceptance based on the different requirements of logic versus memory chips. It also focused on the markets for copper interconnect and low-k dielectric deposition equipment and forecasts.

Key Topics Covered:

Chapter 1 Introduction

Chapter 2 Executive Summary

2.1 Summary of Technical Issues
2.2 Summary of Market Forecasts

Chapter 3 300/450mm Wafer Issues and Trends

3.1 Introduction
3.2 Industry Consortia
3.3 Benefits of 450mm Wafers
3.4 Requirements For IC Manufacturers
3.5 Impact on Automation
3.5.1 Software
3.6 450mm Wafer Issues
3.6.1 Overview
3.6.2 Economic Challenges

Chapter 4 Copper Issues and Trends

4.1 Advantages of Copper
4.2 Copper Processing Challenges
4.3 Metal Deposition
4.3.1 Seed Layer
4.3.2 Bulk Copper Fill
4.4 Barriers
4.5 Planarization
4.6 Metrology
4.7 Competing against Aluminum Damascene
4.8 Copper for 22nm
4.8.1 Low-K and Hard Metal Mask Deposition
4.8.2 Lithography
4.8.3 Etch
4.8.4 Post-etch residue removal
4.8.5 Chemical mechanical polishing
4.9 Equipment Suppliers' Copper Electroplating Products
4.10 Summary
4.10.1 Advantages/Disadvantages of Cu
4.10.2 Processing Issues
4.10.3 Challenges

Chapter 5 Low-K Dielectric Issues and Trends

5.1 Introduction
5.2 Ideal Dielectric
5.3 Types of Low-K Dielectrics
5.3.1 FSG
5.3.2 HSQ
5.3.3 Nanoporous Silica
5.3.4 Spin-on Polymers
5.3.5 BCB
5.3.6 Flowfill
5.3.7 CVD
5.3.8 AF4
5.3.9 PTFE
5.4 Processing Issues
5.5 Summary
5.5.1 Integration Issues
5.5.2 Low-K Dielectric Issues

Chapter 6 Market Analysis

6.1 Semiconductor Market
6.2 Road to Recovery
6.3 Market Forecast Assumptions
6.4 450mm Wafer Market Forecast
6.5 300/450mm Equipment Market
6.5.1 300/450mm Equipment Tools
6.5.2 Factory Automation in 300mm Fab Market
6.6 Copper Processing Equipment Market
6.7 Low-K Dielectric Market

For more information about this report visit

Media Contact:

Laura Wood, Senior Manager 

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